H8SSLASH2224 datasheet(758/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 672 of 982

REJ09B0054-0500

16.4.7

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the

FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is

automatically held low after one frame has been transferred; this timing is synchronized with the

internal clock. Figure 16.19 shows the IRIC set timing and SCL control.

(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)

SCL

SDA

IRIC

User processing

Write to ICDR (transmit)

or read ICDR (receive)

Clear IRIC

Clear

IRIC

Clear IRIC

(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)

SCL

SDA

IRIC

User processing

Clear

IRIC

Write to ICDR (transmit)

or read ICDR (receive)

SCL

SDA

IRIC

User processing

Write to ICDR (transmit)

or read ICDR (receive)

Figure 16.19 IRIC Setting Timing and SCL Control

H8S/2224 Scheda tecnica(PDF) 758 Page - Renesas Technology Corp