H8SSLASH2224 datasheet(756/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 670 of 982

REJ09B0054-0500

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. The transmission procedure and operations in

slave transmit mode are described below.

1. Initialize slave receive mode and wait for slave address reception.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If

the 8th data bit (R/

W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave

transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC

bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the

TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit

9th clock until ICDR data is written, to disable the master device to output the next transfer

clock.

3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the TDRE internal flag is

cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and IRIC

flag are set to 1 again. The slave device sequentially sends the data written into ICDRS in

accordance with the clock output by the master device.

The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR

processing that includes interrupt processing during this period. If a duration sufficient for one

byte of data to be transferred elapses before the IRIC flag is cleared, it will not be possible to

determine that the transfer has completed.

4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.

As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to

determine whether the transfer operation was performed successfully. When one frame of data

has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock

pulse. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS,

transmission starts, and the TDRE internal flag and IRIC flag are set to 1 again. If the TDRE

internal flag has been set to 1, this slave device drives SCL low from the fall of the 9th

transmit clock until data is written to ICDR.

5. To continue transmission, write the next data to be transmitted into ICDR. The TDRE internal

flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing

from the ICDR writing to the IRIC flag clearing should be performed continuously. Prevent

any processing that includes interrupt processing during this period.

Transmit operations can be performed continuously by repeating steps [4] and [5].

6. Clear the IRIC flag to 0.

7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in

the ACKB bit to 0.

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