H8SSLASH2224 datasheet(772/1071 Pages) RENESAS

772 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 686 of 982

REJ09B0054-0500

SLA

DATA2

SLA

DATA3

DATA4

DATA1

I2C bus interface

(Master transmit mode)

Transmit data match

Transmit timing match

• Receive address is ignored

• Automatically transferred to slave

receive mode

• Receive data is recognized as an

address

• When the receive data matches to

the address set in the SAR or SARX

as a slave device.

• Arbitration is lost

• The AL flag in ICSR is set to 1

Transmit data does not match

Other device

(Master transmit mode)

I2C bus interface

(Slave receive mode)

Data contention

Figure 16.27 Diagram of Erroneous Operation Wen Arbitration Is Lost

Though it is prohibited in the normal I2C protocol, the same problem may occur when the

MST bit is erroneously set to 1 and a transition to master mode is occurred during data

transmission or reception in slave mode. In multi-master mode, pay attention to the setting of

the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register

should be set to 1 according to the order below.

(1) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting

the MST bit.

(2) Set the MST bit to 1.

(3) To confirm that the bus was not entered to the busy state while the MST bit is being set,

check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been

set.

16. Note on Wait Operation in Master Mode

When the interrupt request flag (IRIC) is cleared from 1 to 0 between the falling edge of the

7th clock and the falling edge of the 8th clock in master mode using the wait function, a wait

may not be inserted after the falling edge of the 8th clock and 9th clock pulse may be output

continuously.

When using the wait operation, note the following to clear the IRIC flag.

After the IRIC flag is set to 1 at the rising edge of the 9th clock, clear the IRIC falg before the

rising edge of the 7th clock (when the value of the BC2 to BC0 counter is 2 or more).

If the clearing of the IRIC flag is deleyed due to interrupt handling etc. and the value of the BC

counter reaches 1 or 0, confirm that the SCL pin is low and then clear the IRIC flag after the

BC2 to BC0 counter reaches 0 (see figure 16.28).

H8S/2224 Scheda tecnica(PDF) 772 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 772 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL