H8SSLASH2224 datasheet(773/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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773 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 687 of 982

REJ09B0054-0500

SCL

BC2 to BC0

Transmit data

SDA

IRIC flag can not be cleared

IRIC flag can be cleared

IRIC

(sampling

example)

Confirm

SCL = L

IRIC clear

IRIC clear when

BC2 to BC0

≥ 2

Transmit data

Figure 16.28 IRIC Flag Clearing Timing in Wait Operation

17. Interrupt during Module Stop Mode

When the module is stopped in the state that an interrupt is requested, the interrupt source of

the CPU or activation source of the DTC is not cleared. Be sure to enter module stop mode by

disabling the interrupt beforehand.

16.6.1

Module Stop Mode Setting

IIC operation can be disabled or enabled using the module stop control register. The initial setting

is for IIC operation to be halted. Register access is enabled by clearing module stop mode. For

details, refer to section 24, Power-Down Modes.

H8S/2224 Scheda tecnica(PDF) 773 Page - Renesas Technology Corp