H8SSLASH2224 datasheet(771/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 685 of 982

REJ09B0054-0500

13. Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode

When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive

mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the

completion of the transmit or receive operation and a clock may not be output to the SCL bus

line before the ICDR register access operation can take place properly.

When accessing ICDR, always change the setting to the transmit mode before performing a

read operation, and always change the setting to the receive mode before performing a write

operation.

14. Notes on ACKE Bit and TRS Bit in Slave Mode

When using the I2C bus interface, if an address is received in the slave mode immediately after

1 is received as an acknowledge bit (ACKB = 1) in the transmit mode (TRS = 1), an interrupt

may be generated at the rising edge of the 9th clock cycle if the address does not match.

When performing slave mode operations using the IIC bus interface module, make sure to do

the following.

(1) When a 1 is received as an acknowledge bit for the final transmit data after completing a

series of transmit operations, clear the ACKE bit in the ICCR register to 0 to initialize the

ACKB bit to 0.

(2) In the slave mode, change the setting to the receive mode (TRS = 0) before the start

condition is input. To ensure that the switch from the slave transmit mode to the slave

receive mode is accomplished properly, end the transmission as described in figure 16.17.

15. Notes on Arbitration Lost in Master Mode

The I2C bus interface recognizes the data in transmit/receive frame as an address when

arbitration is lost in master mode and a transition to slave receive mode is automatically

carried out.

When arbitration is lost not in the first frame but in the second frame or subsequent frame,

transmit/receive data that is not an address is compared with the value set in the SAR or SARX

figure 16.27.)

In multi-master mode, a bus conflict could happen. When The I2C bus interface is operated in

master mode, check the state of the AL bit in the ICSR register every time after one frame of

data has been transmitted or received.

When arbitration is lost during transmitting the second frame or subsequent frame, take

avoidance measures.

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