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H8S/2224 Scheda tecnica(PDF) 812 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 812 Page - Renesas Technology Corp |
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812 / 1071 page ![]() Section 20 Flash Memory (F-ZTAT Version) Rev. 5.00 Aug 08, 2006 page 726 of 982 REJ09B0054-0500 Bit Bit Name Initial Value R/W Description 2 PV1 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program- verify mode is cancelled. [Setting condition] When FWE = 1 and SWE1 = 1 1E1 0 R/W Erase When this bit is set to 1, and while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 0 P1 0 R/W Program When this bit is set to 1, and while the SWE1 and PSU1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. When FWE = 1, SWE1 = 1, and PSU1 = 1 20.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See section 20.9.3, Error Protection, for details. 6 to 0 — All 0 R Reserved These bits are always read as 0. 20.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. |
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