H8SSLASH2224 datasheet(873/1071 Pages) RENESAS

873 / 1071 page

Section 24 Power-Down Modes

Rev. 5.00 Aug 08, 2006 page 787 of 982

REJ09B0054-0500

24.1

The following registers relates to the power-down modes. For details on system clock control

on low power control register (LPWRCR), refer to section 23.1.2, Low Power Control Register

(LPWRCR). For details on timer control status register (TCSR_1), refer to section 13.3.2, Timer

Control/Status Register (TCSR).

• Standby control register (SBYCR)

• Module stop control register A (MSTPCRA)

• Module stop control register B (MSTPCRB)

• Module stop control register C (MSTPCRC)

• Low power control register (LPWRCR)

• System clock control register (SCKCR)

• Timer control status register (TCSR_1)

24.1.1

Standby Control Register (SBYCR)

SBYCR performs power-down mode control.

Bit

Bit Name

Initial Value

R/W

Description

SSBY

R/W

Software Standby

Specifies transition destination when the SLEEP

instruction is executed.

0: Shifts to sleep mode when the SLEEP instruction

is executed in high-speed mode or medium-speed

mode.

Shifts to subsleep mode when the SLEEP

instruction is executed in subactive mode.

1: Shifts to software standby mode, subactive mode,

and watch mode when the SLEEP instruction is

executed in high-speed mode or medium-speed

mode.

Shifts to watch mode or high-speed mode when

the SLEEP instruction is executed in subactive

mode.

Note that the value of the SSBY bit does not change

even when software standby mode is canceled and

making normal operation mode transition by

executing an external interrupt. To clear this bit, 0

should be written to.

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