H8SSLASH2224 datasheet(877/1071 Pages) RENESAS

877 / 1071 page

Section 24 Power-Down Modes

Rev. 5.00 Aug 08, 2006 page 791 of 982

REJ09B0054-0500

When the SLEEP instruction is executed with the SSBY bit = 1, the LSON bit in LPWRCR = 0,

and the PSS bit in TCSR_1 (WDT_1) = 0, operation shifts to the software standby mode. When

software standby mode is cleared by an external interrupt, medium-speed mode is restored.

When the

RES or MRES pin is set low and medium-speed mode is cancelled, operation shifts to

the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Figure 24.2 shows the timing for transition to and clearance of medium-speed mode.

Note: * Supported only by the H8S/2239 Group.

φ,

Peripheral module clock

Bus master clock

Internal address bus

Internal write signal

Medium-speed mode

SCKCR

Figure 24.2 Medium-Speed Mode Transition and Clearance Timing

24.3

Sleep Mode

24.3.1

Transition to Sleep Mode

When the SLEEP instruction is executed while the SSBY bit in SBYCR = 0 and the LSON bit in

LPWRCR = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the

contents of the CPU’s internal registers are retained. Other peripheral modules do not stop.

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