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H8S/2224 Scheda tecnica(PDF) 940 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 940 Page - Renesas Technology Corp |
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940 / 1071 page ![]() Section 27 Electrical Characteristics Rev. 5.00 Aug 08, 2006 page 854 of 982 REJ09B0054-0500 (1) Clock Timing Table 27.5 lists the clock timing. Table 27.5 Clock Timing Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 74 100 ns Clock high pulse width tCH 25 ns Clock low pulse width tCL 25 ns Clock rise time tCr 10 ns Clock fall time tCf 10 ns Figure 27.10 Oscillation stabilization time at reset (crystal) tOSC1 20 ms Figure 27.11 Oscillation stabilization time in software standby (crystal) tOSC2 8 ms External clock output stabilization delay time tDEXT 500 µs Figure 27.11 32-kHz clock oscillation stabilization time tOSC3 2s Subclock oscillator frequency fSUB 32.768 32.768 kHz Subclock ( φSUB) cycle time tSUB 30.5 30.5 µs |
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