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H8S/2224 Scheda tecnica(PDF) 944 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 944 Page - Renesas Technology Corp |
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944 / 1071 page ![]() Section 27 Electrical Characteristics Rev. 5.00 Aug 08, 2006 page 858 of 982 REJ09B0054-0500 Table 27.9 I2C Bus Timing Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C Standard Value Item Symbol Min Typ Max Unit Test Conditions SCL input cycle time tSCL 12 tcyc SCL input high pulse width tSCLH 3 tcyc SCL input low pulse width tSCLL 5 tcyc SCL, SDA input rise time tSr 7.5* tcyc SCL, SDA input fall time tSf 300 ns SCL, SDA input spike pulse elimination time tSP 1tcyc SDA input bus free time tBUF 5 tcyc Start condition input hold time tSTAH 3 tcyc Retransmission start condition input setup time tSTAS 3 tcyc Stop condition input setup time tSTOS 3 tcyc Data input setup time tSDAS 0.5 tcyc Data input hold time tSDAH 0 ns SCL, SDA load capacitance Cb 400 pF Figure 27.7 Note: * Can be 7.5 tcyc or 17.5 tcyc depending on the clock used in the I 2C module. For details, see section 16.6, Usage Notes. |
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