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H8S/2224 Scheda tecnica(PDF) 981 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 981 Page - Renesas Technology Corp |
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981 / 1071 page ![]() Section 27 Electrical Characteristics Rev. 5.00 Aug 08, 2006 page 895 of 982 REJ09B0054-0500 Table 27.29 Bus Drive Characteristics Condition A (F-ZTAT version): VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Applicable Pins: SCL1 and SCL0, SDA1 and SDA0 Item Symbol Min Typ Max Unit Test Conditions VT – VCC × 0.3 VCC = 2.7 V to 5.5 V VT + VCC × 0.7 VCC = 2.7 V to 5.5 V 0.4 VCC = 4.0 V to 5.5 V Schmitt trigger input voltage VT + – VT– VCC × 0.05 V VCC = 2.7 V to 4.0 V Input high voltage VIH VCC × 0.7 VCC + 0.5 V VCC = 2.7 V to 5.5 V Input low voltage VIL –0.5 VCC × 0.3 V VCC = 2.7 V to 5.5 V 0.5 IOL = 8 mA, VCC = 4.0 V to 5.5 V Output low voltage VOL 0.4 V IOL = 3 mA Input capacitance Cin 20 pF Vin = 0 V, f = 1 MHz, Ta = 25°C Three-state leakage current (off state) | ITSI | 1.0 µA Vin = 0.5 to VCC – 0.5 V SCL, SDA output fall time tOf 20 + 0.1 Cb 250 ns VCC = 2.7 V to 5.5 V Note: * If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 2.0 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref ≤ AVCC. |
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