H8SSLASH2224 datasheet(983/1071 Pages) RENESAS

983 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 897 of 982

REJ09B0054-0500

(1) Clock Timing

Table 27.30 lists the clock timing

Table 27.30 Clock Timing

Condition A (F-ZTAT version):

VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Conditions A, B

Item

Symbol

Min

Typ

Max

Unit

Test

Conditions

Clock cycle time

tcyc



500

Clock high pulse width

tCH



Clock low pulse width

tCL



Clock rise time

tCr



Clock fall time

tCf



Figure 27.10

Reset oscillation stabilization

time (crystal)

tOSC1



Figure 27.11

Software standby oscillation

stabilization time (crystal)

tOSC2



External clock output stabilization

delay time

tDEXT

500



µs

Figure 27.11

Subclock oscillation stabilization

time

tOSC3



Subclock oscillator frequency

fSUB



32.768



kHz

Subclock (

φSUB) cycle time

tSUB



30.5



µs

H8S/2224 Scheda tecnica(PDF) 983 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 983 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL