H8SSLASH2224 datasheet(1002/1071 Pages) RENESAS

1002 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 916 of 982

REJ09B0054-0500

Table 27.42 Clock Timing

Condition A (F-ZTAT version and masked ROM version):

VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,

Vref = 2.7 V to AVCC, VSS =AVSS = 0 V,

φ = 32.768 kHz, 2 to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (F-ZTAT version):

VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS =AVSS = 0 V,

φ = 32.768 kHz, 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications)

Condition C (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition A

Conditions B, C

Item

Symbol Min

Typ

Max

Min

Typ

Max

Unit

Test

Conditions

Clock cycle time

tcyc



500

160



500

Clock high pulse width

tCH



Clock low pulse width

tCL



Clock rise time

tCr



Clock fall time

tCf



Figure 27.10

Oscillation stabilization

time at reset (crystal)

tOSC1



Figure 27.11

Oscillation stabilization

time in software standby

(crystal)

tOSC2



External clock output

stabilization delay time

tDEXT

500



1000



µs

Figure 27.11

Subclock oscillation

stabilization time

tOSC3



Subclock oscillator

frequency

fSUB



32.768



32.768



kHz

Subclock (

φSUB) cycle

time

tSUB



30.5



30.5



µs

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