H8SSLASH2224 datasheet(1006/1071 Pages) RENESAS

1006 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 920 of 982

REJ09B0054-0500

(4) Timing of On-Chip Peripheral Modules

Table 27.45 lists the timing of on-chip peripheral modules. Table 27.46 lists the I2C bus timing.

Table 27.45 Timing of On-Chip Peripheral Modules

Condition A (F-ZTAT version and masked ROM version):

VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,

Vref = 2.7 V to AVCC, VSS =AVSS = 0 V,

φ = 32.768 kHz, 2 to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (F-ZTAT version):

VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS =AVSS = 0 V,

φ = 32.768 kHz, 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications)

Condition C (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition A

Conditions B, C

Item

Symbol

Min

Max

Min

Max

Unit

Test

Conditions

I/O port* Output data delay time

tPWD



100



150

Figure 27.24

Input data setup time

tPRS



Input data hold time

tPRH



TPU

Timer output delay time

tTOCD



100



150

Figure 27.25

Timer input setup time

tTICS



Timer clock input setup

time

tTCKS



Figure 27.26

Single edge tTCKWH

1.5



1.5



tcyc

Timer clock

pulse width Both edges t

TCKWL

2.5



2.5



TMR

Timer output delay time

tTMOD



100



150

Figure 27.27

Timer reset input setup

time

tTMRS



Figure 27.29

Timer clock input setup

time

tTMCS



Figure 27.28

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