H8SSLASH2224 datasheet(1004/1071 Pages) RENESAS

1004 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 918 of 982

REJ09B0054-0500

(3) Bus Timing

Table 27.44 lists the bus timing.

Table 27.44 Bus Timing

Condition A (F-ZTAT version and masked ROM version):

VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,

Vref = 2.7 V to AVCC, VSS =AVSS = 0 V,

φ = 2 to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (F-ZTAT version):

VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS =AVSS = 0 V,

φ = 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications)

Condition C (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS = AVSS = 0 V,

φ = 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition A

Conditions B, C

Test

Item

Symbol

Min

Max

Min

Max

Unit

Conditions

Address delay time

tAD



Address setup time

tAS

0.5

× tcyc −



0.5

× tcyc

− 60



Address hold time

tAH

0.5

× tcyc −



0.5

× tcyc

− 30



Figures 27.14

to 27.18

CS delay time

tCSD



AS delay time

tASD



RD delay time 1

tRSD1



RD delay time 2

tRSD2



Read data setup time

tRDS



Read data hold time

tRDH



Read data access time 1

tACC1



1.0

× tcyc

− 65



1.0

× tcyc

− 90

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