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H8S/2224 Scheda tecnica(PDF) 180 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 180 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 5.00 Aug 08, 2006 page 94 of 982
REJ09B0054-0500
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Table 2.13 Effective Address Calculation
No
1
Offset
1
2
4
r
op
31
0
31
23
2
3
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
4
r
op
disp
r
op
rm
op
rn
31
0
31
0
r
op
Don't care
31
23
31
0
Don't care
31
0
disp
31
0
31
0
31
23
31
0
Don't care
31
23
31
0
Don't care
24
24
24
24
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
· Register indirect with post-increment @ERn+
· Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand Size
Byte
Word
Longword
Operand is general register contents.



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