H8SSLASH2224 datasheet(182/1071 Pages) RENESAS

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Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 96 of 982

REJ09B0054-0500

2.8

Processing States

The H8S/2000 CPU has five main processing states: the reset state, exception handling state,

program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state

transitions.

• Reset State

In this state, the CPU and all on-chip peripheral modules are initialized and not operating.

When the

RES input goes low, all current processing stops and the CPU enters the reset state.

All interrupts are masked in the reset state. Reset exception handling starts when the

RES

signal changes from low to high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

• Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.

The CPU fetches a start address (vector) from the exception vector table and branches to that

address. For further details, refer to section 4, Exception Handling.

• Program Execution State

In this state, the CPU executes program instructions in sequence.

• Bus-Released State

In a product which has a DMA controller (DMAC)* or data transfer controller (DTC), the bus-

released state occurs when the bus has been released in response to a bus request from a bus

master other than the CPU.

While the bus is released, the CPU halts operations.

• Power-down State

This is a power-down state in which the CPU stops operating. The program stop state occurs

when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further

details, refer to section 24, Power-Down Modes.

Note: * Supported only by the H8S/2239 Group.

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