H8SSLASH2224 datasheet(183/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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183 / 1071 page

Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 97 of 982

REJ09B0054-0500

Exception handling state

Bus-released state

Hardware standby mode*

Software standby mode

Reset state*

Sleep mode

Power-down state*

Program execution state

End of bus request

Bus request

Interrupt

request

External interrupt request

RES = High,

MRES = High

STBY = High, RES = Low

End

bus

reque

Bus

request

SLEEP instruction,

SSBY = 0

SLEEP instruction,

SSBY = 1

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs whenever

RES

goes low. A transition can also be made to the reset state when the watchdog timer overflows.

From any state except hardware standby mode and power-on reset state, a transition to the manual

reset state occurs whenever

MRES goes low.

From any state, a transition to hardware standby mode occurs when

STBY goes low.

Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.

See section 24, Power-Down Modes.

Figure 2.13 State Transitions

H8S/2224 Scheda tecnica(PDF) 183 Page - Renesas Technology Corp