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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 234 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 234 Page - Renesas Technology Corp |
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234 / 1071 page  Section 5 Interrupt Controller Rev. 5.00 Aug 08, 2006 page 148 of 982 REJ09B0054-0500 Yes Program execution status Interrupt generated? NMI Level 6 interrupt? Mask level 5 or below? Level 7 interrupt? Mask level 6 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt? Mask level 0? Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.5.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. |
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