H8SSLASH2224 datasheet(238/1071 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 152 of 982

REJ09B0054-0500

DMAC*

Selection

circuit

DTCER

DTVECR

Control logic

Determination of

priority

CPU

DTC

Selection

signal

IRQ

interrupt

Internal

peripheral

function

modules

Clear

signal

Interrupt controller

I, I2 to I0

Interrupt source

clear signal

Interrupt request

DTC start

request vector

number

CPU interrupt

request vector

number

SWDTE

clear signal

Clear signal

Note: * Supported only by the H8S/2239 Group.

Figure 5.8 DTC and DMAC* Interrupt Control

(1) Interrupt Source Selection

The DMAC* startup sources are directly input to each channel. The startup source for each

DMAC* channel is selected by the DMACR DTF3 to DTF0 bits. Whether or not the selected

startup source is managed by the DMAC* can be selected with the DMABCR DTA bit. If the

DTA bit is set to 1, the interrupt source that has become the DMAC* startup source will not be

either a DTC startup source or a CPU interrupt source.

Interrupt sources other than the interrupt managed by the DMAC* are selected to be DTC startup

sources or CPU interrupt requests by the DTC DTCERA to DTCERF DTCE bits.

After a DTC data transfer, a CPU interrupt can be requested by clearing the DTCE bit to 0 by

specifying that with the DTC MRB DISEL bit.

Note that when the DTC has performed the stipulated number of data transfers and the transfer

counter has become 0, the DTCE bit can be cleared to 0 and a CPU interrupt can be requested.

Note: * Supported only by the H8S/2239 Group.

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