H8SSLASH2224 datasheet(237/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 151 of 982

REJ09B0054-0500

Table 5.8

Number of States in Interrupt Handling Routine Execution Status

Object of Access

External Device

8 Bit Bus

16 Bit Bus

Symbol

Internal

Memory

2-State

Access

3-State

Access

2-State

Access

3-State

Access

Instruction fetch

6 + 2 m

3 + m

Branch address read

Stack manipulation

Legend:

m: Number of wait states in an external device access.

5.5.6

DTC and DMAC* Activation by Interrupt

The DTC and DMAC* can be started by interrupts. The following settings are required for this

operation.

1. Interrupt request to the CPU

2. Start request to the DTC

3. Start request to the DMAC*

4. Multiple specification of items 1 to 3.

See section 8, DMA Controller (DMAC)*, and section 9, Data Transfer Controller (DTC) for

more information on the interrupts that can start the DTC and DMAC*.

Figure 5.8 shows the block diagram of the DTC, DMAC*, and interrupt controller circuits.

Note: * Supported only by the H8S/2239 Group.

H8S/2224 Scheda tecnica(PDF) 237 Page - Renesas Technology Corp