TMS320VC5505 datasheet(33/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

Table 3-19. Regulators and Power Management Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Regulators

[Not supported on this device. Reserved for compatibility with future devices].

For proper device operation, this pin must be connected to an ~ 1.0 mF decoupling

DSP_LDOO

E10

capacitor to VSS. For more detailed information, see Section 6.3.3, Power-Supply

Decoupling.

[Not supported on this device. Reserved for compatibility with future devices].

DSP_LDOI

F14

For proper device operation, this pin must be connected to the same supply as the

ANA_LDOI pin (B12).

[Not supported on this device. Reserved for compatibility with future devices].

For proper device operation, this pin must be tied to ground (VSS). For future device

–

DSP_LDO_EN

D12

family pin compatibility, board designs should have this pin layout with a zero-

Ω

ANA_LDOI

resistor to ANA_LDOI and a zero-

Ω resistor to ground. For VC5505 , only the

zero-

Ω resistor to ground should be populated.

[Not supported on this device. Reserved for compatibility with future devices].

For proper device operation, this pin must be connected to the same supply as the

–

ANA_LDOI pin (B12). For future device family pin compatibility, board designs

DSP_LDO_V

D13

ANA_LDOI

should have this pin layout with a zero-

Ω resistor to ANA_LDOI and a zero-Ω

resistor to ground. For VC5505 , only the zero-

Ω resistor to ANA_LDOI should be

populated.

[Not supported on this device. Reserved for compatibility with future devices].

USB_LDOO

F12

For proper device operation, this pin must be left unconnected.

[Not supported on this device. Reserved for compatibility with future devices].

USB_LDOI

F13

For proper device operation, this pin must be connected to the same supply as the

ANA_LDOI pin (B12).

Analog LDO output. This output provides up to 3 mA of current regulated to 1.3 V

(see the ISD parameter in Section 5.3, Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating Temperature).

ANA_LDOO

A12

For proper device operation, this pin must be connected to an ~ 1.0 mF decoupling

capacitor to VSS. For more detailed information, see Section 6.3.3, Power-Supply

Decoupling.

Analog LDO input. This input pin must be connected to a power supply with a

ANA_LDOI

B12

voltage range of 1.8 V to 3.6 V. It supplies power for the ANA_LDO, the bandgap

reference generator circuits, and is the I/O supply for some input pins.

Bandgap reference filter signal. For proper device operation, this pin needs to be

bypassed with a 0.1 mF capacitor to analog ground (VSSA_ANA).

BG_CAP

B13

This external capacitor provides filtering for stable reference voltages & currents

generated by the bandgap circuit. The bandgap produces the references for use by

the System PLL, SAR, and POR circuits.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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