TMS320VC5505 datasheet(71/135 Pages) TI

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INTx

TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

6.8

Wake-up Events, Interrupts, and XF

The VC5505 device has a number of interrupts to service the needs of its peripherals. The interrupts can

be selectively enabled or disabled.

6.8.1

Interrupts Electrical Data/Timing

Table 6-7. Timing Requirements for Interrupts(1) (see Figure 6-11)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

UNIT

MIN

MAX

tw(INTH)

Pulse duration, interrupt high CPU active

tw(INTL)

Pulse duration, interrupt low CPU active

(1)

P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns.

Figure 6-11. External Interrupt Timings

6.8.2

Wake-Up From IDLE Electrical Data/Timing

Table 6-8. Timing Requirements for Wake-Up From IDLE (see Figure 6-12)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

UNIT

MIN

MAX

tw(WKPL)

Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1

Table 6-9. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From

IDLE(1) (2) (3)

(see Figure 6-12)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

PARAMETER

UNIT

MIN

TYP

MAX

IDLE3 Mode with SYSCLKDIS = 1,

WAKEUP or INTx event, CLK_SEL =

td(WKEVTH-C

Delay time, Wake-Up event high to

IDLE3 Mode with SYSCLKDIS = 1,

KLGEN)

CPU active

WAKEUP or INTx event, CLK_SEL =

IDLE2 Mode; INTx event

(1)

P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, P = 10 ns.

(2)

C = 1/RTCCLK= 30.5 ms. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.

(3)

Assumes the internal LDOs are used with a 0.1uF bandgap capacitor.

Peripheral Information and Electrical Specifications

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