TMS320VC5505 datasheet(12/135 Pages) TI

12 / 135 page

00010000h

64KMinus192Bytes

DARAM

(D)

00090000h

SARAM

256KBytes

External-CS2Space

(C)

02000000h

03000000h

04000000h

05000000h

050E0000h

128KBytes Asynchronous(ifMPNMC=1)

128KBytesROM(ifMPNMC=0)

External-CS3Space

(C)

External-CS4Space

(C)

External-CS5Space

(C)

BLOCKSIZE

DMA/USB/LCD

BYTE ADDRESS(A)

ROM

(ifMPNMC=0)

External-CS5

fMPNMC=1)

(C)

Space

1MMinus128KBytes Asynchronous

1MBytes Asynchronous

2MBytes Asynchronous

4MBytes Asynchronous

MEMORY BLOCKS

000100C0h

MMR(Reserved)

(B)

01000000h

Reserved

8MMinus320KBytes

050FFFFFh

000000h

010000h

800000h

C00000h

E00000h

F00000h

FE0000h

CPUBYTE

ADDRESS(A)

0000C0h

050000h

FFFFFFh

TMS320VC5505

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

www.ti.com

3.3

Memory Map Summary

The VC5505 provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and

external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two

accesses to a given block during the same cycle. The VC5505 supports 8 blocks of 4K words of

dual-access RAM. The on-chip, single-access RAM allows one access to a given block per cycle. The

VC5505 supports 32 blocks of 4K words of single-access RAM.

The remainder of the memory map is divided into reserved areas, four external spaces, and on-chip ROM.

Each external space has a chip select decode signal (called CS[2:5]) that indicates an access to the

selected space. The external memory interface (EMIF) supports access to asynchronous memories such

as SRAM, NAND, or NOR.

The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the

four DMA controllers, LCD, and USB (see Figure 3-1).

Address shown represents the first byte address in each block.

The first 192 bytes are reserved for memory-mapped registers (MMRs).

Out of the four DMA controllers, only DMA controller 3 has access to the external memory space.

The USB and LCD controllers do not have access to DARAM.

Figure 3-1. TMS320VC5505 Memory Map Summary

3.4

Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in

the smallest possible package. Pin multiplexing is controlled using software programmable register

settings. For more information on pin muxing, see Section 4.7, Multiplexed Pin Configurations of this

document.

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