TMS320VC5505 datasheet(64/135 Pages) TI

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CLKIN

TMS320VC5505

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

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The PLL has a lock time requirements that must be followed. The PLL lock time is the amount of time

needed for the PLL to complete its phase-locking sequence.

6.5.2

Clock PLL Considerations With External Clock Sources

If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single

clean power supply should power both the VC5505 device and the external clock oscillator circuit. The

minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see

Section 6.5.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 6.5.3, Clock

PLL Electrical Data/Timing (Input and Output Clocks).

6.5.3

Clock PLL Electrical Data/Timing (Input and Output Clocks)

Table 6-4. Timing Requirements for CLKIN(1) (2) (see Figure 6-7)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

88.577,

Cycle time, external

83.333,

tc(CLKIN)

clock driven on

16.67

CLKIN

81.380

Pulse width, CLKIN

tw(CLKINH)

0.466 * tc(CLKIN)

high

Pulse width, CLKIN

tw(CLKINL)

0.466 * tc(CLKIN)

low

Transition time,

tt(CLKIN)

0.34 * tc(CLKIN)

CLKIN

(1)

The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for

CPU operating frequency.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

Figure 6-7. CLKIN Timing

Peripheral Information and Electrical Specifications

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