TMS320VC5505 datasheet(67/135 Pages) TI

67 / 135 page

TMS320VC5505

www.ti.com

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

6.7

Reset

Supports only one type of reset, device reset.

The VC5505 has two main types of reset: hardware reset and software reset.

Hardware reset is responsible for initializing all key states of the device. It occurs whenever the RESET

pin is asserted or when the internal power-on-reset (POR) circuit deasserts an internal signal called

POWERGOOD. VC5505 device's internal POR is a voltage comparator that monitors the DSP_LDOO pin

voltage and generates the internal POWERGOOD signal. POWERGOOD is asserted when the

DSP_LDOO voltage is above a minimum threshold voltage provided by the bandgap. On VC5505 , the

voltage comparator circuit is present and active in the POR circuit even though the DSP_LDO is not

currently supported. The RESET pin and the POWERGOOD signal are internally combined with a logical

AND gate to produce an (active low) hardware reset (see Figure 6-9, Power-On Reset Timing

Requirements and Figure 6-10, Reset Timing Requirements).

There are two types of software reset: the CPU's software reset instruction and the software control of the

peripheral reset signals. For more information on the CPU's software reset instruction, see the

TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073). In all VC5505

documentation, all references to "reset" refer to hardware reset. Any references to software reset will

explicitly state software reset.

The VC5505 RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC

core. This POR monitors the voltage of CVDD_RTC and resets the RTC registers when power is first applied

to the RTC core.

6.7.1

Power-On Reset (POR) Circuits

The VC5505 device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another

for the rest of the chip (MAIN POR).

6.7.1.1

RTC Power-On Reset (POR)

The RTC POR ensures that the flip-flops in the CVDD_RTC power domain have an initial state upon

powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC

time registers need to be initialized with the current time and date when power is first applied.

6.7.1.2

Main Power-On Reset (POR)

The VC5505 device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until

specific voltages have reached predetermined levels. The output of the POR circuit, POWERGOOD, is

held low until the following conditions are satisfied:

•

ANA_LDOI is powered and the bandgap is active for at least approximately 8 ms

•

VDD_ANA is powered for at least approximately 4 ms

•

DSP_LDOO is powered and above a threshold of approximately 900 mV (see Note:)

Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal

is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's

global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global

reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,

see Section 4.4, Boot Sequence.

Note: The DSP_LDO is not supported on VC5505 device, but it's output voltage is still monitored by the

MAIN POR and must reach, and remain, higher than the POR's threshold for the POWERGOOD signal to

be high. The DSP_LDOO pin must be left floating and be properly bypassed as specified in the

DSP_LDOO entry in Table 3-19, Regulators and Power Management Terminal Functions. By leaving this

pin floating, the VC5505 's internal circuits provide the necessary voltage above the POR's threshold for

POWERGOOD.

Peripheral Information and Electrical Specifications

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