TMS320VC5505 datasheet(23/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

Table 3-11. Serial Peripheral Interface (SPI) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Serial Port Interface (SPI)

This pin is multiplexed between LCD Bridge and SPI.

LCD_CS0_E0/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_CS0

For SPI, this pin is SPI chip select SPI_CS0.

LCD_D[9]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_FS/

IPD

Mux control via the PPMODE bits in the EBSR.

P11

I/O/Z

GP[19]/

DVDDIO

For SPI, this pin is SPI chip select SPI_CS0.

SPI_CS0

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_CS1_E1/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_CS1

For SPI, this pin is SPI chip select SPI_CS1.

This pin is multiplexed between LCD Bridge and SPI.

LCD_RW_WRB/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_CS2

For SPI, this pin is SPI chip select SPI_CS2.

This pin is multiplexed between LCD Bridge and SPI.

LCD_RS/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_CS3

For SPI, this pin is SPI chip select SPI_CS3.

This pin is multiplexed between LCD Bridge and SPI.

LCD_EN_RDB/

O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_CLK

For SPI, this pin is clock output SPI_CLK.

LCD_D8]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_CLK/

IPD

Mux control via the PPMODE bits in the EBSR.

N10

GP[18]/

DVDDIO

For SPI, this pin is clock output SPI_CLK.

SPI_CLK

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_D[1]/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_TX

For SPI, this pin is SPI transmit data output.

LCD_D[11]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_DX/

IPD

Mux control via the PPMODE bits in the EBSR.

P12

I/O/Z

GP[27]/

DVDDIO

For SPI, this pin is SPI transmit data output.

SPI_TX

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_D[0]/

I/O/Z

DVDDIO

Mux control via the PPMODE bits in the EBSR.

SPI_RX

For SPI this pin is SPI receive data input.

LCD_D[10]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_RX/

IPD

Mux control via the PPMODE bits in the EBSR.

N11

I/O/Z

GP[20]/

DVDDIO

For SPI this pin is SPI receive data input.

SPI_RX

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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