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TMS320VC5505 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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TMS320VC5505 Scheda tecnica(HTML) 3 Page - Texas Instruments |
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3 / 135 page ![]() PLL/Clock Generator Power Management Pin Multiplexing JTAGInterface 64KBDARAM 256KBSARAM 128KBROM SwitchedCentralResource(SCR) Input Clock(s) FFT Hardware Accelerator C55x™ DSP CPU DSP System LCD Bridge Display I S (x4) 2 I C 2 SPI UART SerialInterfaces GP Timer (x2) System 10-Bit SAR ADC App-Spec USB2.0 PHY (HS) [DEVICE] RTC Connectivity NAND,NOR, SRAM Program/DataStorage MMC/SD (x2) Peripherals DMA (x4) Interconnect GP Timer and/orWD TMS320VC5505 www.ti.com SPRS503B – JUNE 2009 – REVISED JANUARY 2010 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the VC5505 device. Figure 1-1. TMS320VC5505 Functional Block Diagram Copyright © 2009–2010, Texas Instruments Incorporated Fixed-Point Digital Signal Processor 3 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 |
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