TMS320VC5505 datasheet(63/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective

series resistance (ESR) specified in Table 6-2. The load capacitors, C1 and C2 are the total capacitance

of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually

approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal

manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete

components used to implement the oscillator circuit should be placed as close as possible to the

associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.

Table 6-2. Input Requirements for Crystal on the 12-MHz USB Oscillator

PARAMETER

MIN

NOM

MAX

UNIT

Start-up time (from power up until oscillating at stable frequency of 12 MHz)(1)

0.100

Oscillation frequency

MHz

ESR

100

Ω

Frequency stability(2)

±100

ppm

Maximum shunt capacitance

Maximum crystal drive

330

(1)

The startup time is highly dependent on the ESR and the capacitive load of the crystal.

(2)

If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.

6.5

Clock PLLs

The VC5505 DSP uses a software-programmable PLL to generate frequencies required by the CPU,

DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC

on-chip oscillator (as specified through the CLK_SEL pin).

6.5.1

PLL Device-Specific Information

There is a minimum and maximum operating frequency for CLKIN, PLLOUT, and the system clock

(SYSCLK). The system clock generator must be configured not to exceed any of these constraints

documented in this section (certain combinations of external clock inputs, internal dividers, and PLL

multiply ratios might not be supported).

Table 6-3. PLLC1 Clock Frequency Ranges

CVDD = 1.05 V

CVDD = 1.3 V

CLOCK SIGNAL NAME

UNIT

MIN

MAX

MIN

MAX

11.2896

CLKIN(1)

MHz

12.288

RTC Clock

32.768

KHz

PLLIN

32.768

170

32.768

170

KHz

PLLOUT

120

MHz

SYSCLK

0.032768

100

MHz

PLL_LOCKTIME

(1)

These CLKIN values are used when the CLK_SEL pin = 1.

Peripheral Information and Electrical Specifications

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