TMS320VC5505 datasheet(19/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

Table 3-8. External Memory Interface (EMIF) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)

Note: When accessing 8-bit Asynchronous memory, pins EM_A[20:0] should be

connected to memory address pins [22:2] and EM_BA[1:0] should be connected to

memory addresss pins [1:0]. For 16-bit Asynchronous memory, pins EM_A[20:0]

should be connected to memory address pins [20:1] and EM_BA[1] should be

connected to memory addresss pin [0].

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 20.

EM_A[20]/GP[26]

I/O/Z

DVDDEMIF

Mux control via the A20_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 19.

EM_A[19]/GP[25]

I/O/Z

DVDDEMIF

Mux control via the A19_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 18.

EM_A[18]/GP[24]

I/O/Z

DVDDEMIF

Mux control via the A18_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 17.

EM_A[17]/GP[23]

I/O/Z

DVDDEMIF

Mux control via the A17_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 16.

EM_A[16]/GP[22]

I/O/Z

DVDDEMIF

Mux control via the A16_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

external address pin 15.

EM_A[15]/GP[21]

I/O/Z

DVDDEMIF

Mux control via the A15_MODE bit in the EBSR (see Figure 4-2).

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

EM_A[14]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 14.

EM_A[13]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 13.

This pin is the EMIF external address pin 12. When interfacing with NAND Flash,

EM_A[12]/(CLE)

I/O/Z

DVDDEMIF

this pin also acts as Command Latch Enable (CLE).

This pin is the EMIF external address pin 11. When interfacing with NAND Flash,

EM_A[11]/(ALE)

I/O/Z

DVDDEMIF

this pin also acts as Address Latch Enable (ALE).

EM_A[10]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 10.

EM_A[9]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 9.

EM_A[8]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 8.

EM_A[7]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 7.

EM_A[6]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 6.

EM_A[5]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 5.

EM_A[4]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 4.

EM_A[3]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 3.

EM_A[2]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 2.

EM_A[1]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 1.

EM_A[0]

I/O/Z

DVDDEMIF

This pin is the EMIF external address pin 0.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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