TMS320VC5505 datasheet(83/135 Pages) TI

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TMS320VC5505

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SPRS503B – JUNE 2009 – REVISED JANUARY 2010

6.10 Multimedia Card/Secure Digital (MMC/SD)

The VC5505 includes two MMC/SD controllers which are compliant with MMC V3.31, Secure Digital Part 1

Physical Layer Specification V2.0, and Secure Digital Input Output (SDIO) V3.3 specifications. The

MMC/SD card controller supports these industry standards and assumes the reader is familiar with these

standards.

Each VC5505 MMC/SD Controller has the following features:

•

Multimedia Card/Secure Digital (MMC/SD) protocol support

•

Programmable clock frequency

•

512 bit Read/Write FIFO to lower system overhead

•

Slave DMA transfer capability

The MMC/SD card controller transfers data between the CPU and DMA controller on one side and

MMC/SD card on the other side. The CPU and DMA controller can read/write the data in the card by

accessing the registers in the MMC/SD controller.

The MMC/SD controller on this device, does not support the SPI mode of operation.

6.10.1

MMC/SD Peripheral Register Description(s)

Table 6-16 and Table 6-17 shows the MMC/SD registers. The MMC/SD0 registers start at address

0x3A00 and the MMC/SD1 registers start at address 0x3B00.

Peripheral Information and Electrical Specifications

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