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TMS320VC5505 Scheda tecnica(PDF) 93 Page - Texas Instruments |
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TMS320VC5505 Scheda tecnica(HTML) 93 Page - Texas Instruments |
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93 / 135 page ![]() 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 TMS320VC5505 www.ti.com SPRS503B – JUNE 2009 – REVISED JANUARY 2010 Figure 6-22. I2C Receive Timings Table 6-23. Switching Characteristics for I2C Timings(1) (see Figure 6-23) CVDD = 1.05 V CVDD = 1.3 V NO. PARAMETER STANDARD UNIT FAST MODE MODE MIN MAX MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs Delay time, SCL high to SDA low (for a repeated START 17 td(SCLH-SDAL) 4.7 0.6 µs condition) Delay time, SDA low to SCL low (for a START and a repeated 18 td(SDAL-SCLL) 4 0.6 µs START condition) 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 ns 22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low 0 0 0.9 µs Pulse duration, SDA high between STOP and START 23 tw(SDAH) 4.7 1.3 µs conditions 20 + 0.1Cb 24 tr(SDA) Rise time, SDA(2) 1000 300 ns (1) 20 + 0.1Cb 25 tr(SCL) Rise time, SCL(2) 1000 300 ns (1) 20 + 0.1Cb 26 tf(SDA) Fall time, SDA(2) 300 300 ns (1) 20 + 0.1Cb 27 tf(SCL) Fall time, SCL(2) 300 300 ns (1) 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF (1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. (2) The rise/fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb) and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified. Copyright © 2009–2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 93 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 |
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