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Motore di ricerca datesheet componenti elettronici |
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TMS320VC5505 Scheda tecnica(PDF) 73 Page - Texas Instruments |
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TMS320VC5505 Scheda tecnica(HTML) 73 Page - Texas Instruments |
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73 / 135 page  TMS320VC5505 www.ti.com SPRS503B – JUNE 2009 – REVISED JANUARY 2010 • NAND Flash memories • NOR Flash memories The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF (EM_CS[5:2]). Each chip select has the following individually programmable attributes: • Data bus width • Read cycle timings: setup, hold, strobe • Write cycle timings: setup, hold, strobe • Bus turn around time • Extended Wait Option With Programmable Timeout • Select Strobe Option • NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes 6.9.2 EMIF Peripheral Register Description(s) Table 6-11 shows the EMIF registers. Table 6-11. External Memory Interface (EMIF) Peripheral Registers(1) HEX ADDRESS ACRONYM REGISTER NAME RANGE 1000h REV Revision Register 1001h STATUS Status Register 1004h AWCCR1 Asynchronous Wait Cycle Configuration Register 1 1005h AWCCR2 Asynchronous Wait Cycle Configuration Register 2 1010h ACS2CR1 Asynchronous CS2 Configuration Register 1 1011h ACS2CR2 Asynchronous CS2 Configuration Register 2 1014h ACS3CR1 Asynchronous CS3 Configuration Register 1 1015h ACS3CR2 Asynchronous CS3 Configuration Register 2 1018h ACS4CR1 Asynchronous CS4 Configuration Register 1 1019h ACS4CR2 Asynchronous CS4 Configuration Register 2 101Ch ACS5CR1 Asynchronous CS5 Configuration Register 1 101Dh ACS5CR2 Asynchronous CS5 Configuration Register 2 1040h EIRR EMIF Interrupt Raw Register 1044h EIMR EMIF Interrupt Mask Register 1048h EIMSR EMIF Interrupt Mask Set Register 104Ch EIMCR EMIF Interrupt Mask Clear Register 1060h NANDFCR NAND Flash Control Register 1064h NANDFSR1 NAND Flash Status Register 1 1065h NANDFSR2 NAND Flash Status Register 2 1068h PGMODECTRL1 Page Mode Control Register 1 1069h PGMODECTRL2 Page Mode Control Register 2 1070h NCS2ECC1 NAND Flash CS2 1-Bit ECC Register 1 1071h NCS2ECC2 NAND Flash CS2 1-Bit ECC Register 2 1074h NCS3ECC1 NAND Flash CS3 1-Bit ECC Register 1 1075h NCS3ECC2 NAND Flash CS3 1-Bit ECC Register 2 1078h NCS4ECC1 NAND Flash CS4 1-Bit ECC Register 1 (1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable word accesses to the EMIF registers. Copyright © 2009–2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 73 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 |
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