TMS320VC5505 datasheet(22/135 Pages) TI

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TMS320VC5505

SPRS503B – JUNE 2009 – REVISED JANUARY 2010

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Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Interface 2 (I2S2)

LCD_D[11]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_DX/

IPD

For I2S, it is I2S2 transmit data output I2S2_DX.

P12

I/O/Z

GP[27]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

SPI_TX

enabled or disabled via the PDINHIBR3 register.

LCD_D8]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_CLK/

IPD

For I2S, it is I2S2 clock input/output I2S2_CLK.

N10

I/O/Z

GP[18]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

SPI_CLK

enabled or disabled via the PDINHIBR3 register.

LCD_D[10]/

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

I2S2_RX/

IPD

For I2S, it is I2S2 receive data input I2S2_RX.

N11

I/O/Z

GP[20]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

SPI_RX

enabled or disabled via the PDINHIBR3 register.

LCD_D[9]/

This pin is multiplexed between LCD Bridge, I2S2, and GPIO.

I2S2_FS/

IPD

For I2S, it is I2S2 frame synchronization input/output I2S2_FS.

P11

I/O/Z

GP[19]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

SPI_CS0

enabled or disabled via the PDINHIBR3 register.

Interface 3 (I2S3)

LCD_D[15]/

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

UART_TXD/

IPD

For I2S, it is I2S3 transmit data output I2S3_DX.

P14

I/O/Z

GP[31]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

I2S3_DX

enabled or disabled via the PDINHIBR3 register.

LCD_D[12]/

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

UART_RTS/

IPD

For I2S, it is I2S3 clock input/output I2S3_CLK.

N12

I/O/Z

GP[28]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

I2S3_CLK

enabled or disabled via the PDINHIBR3 register.

LCD_D[14]/

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

UART_RXD/

IPD

For I2S, it is I2S3 receive data input I2S3_RX.

N13

I/O/Z

GP[30]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

I2S3_RX

enabled or disabled via the PDINHIBR3 register.

LCD_D[13]/

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

UART_CTS/

IPD

For I2S, it is I2S3 frame synchronization input/output I2S3_FS.

P13

I/O/Z

GP[29]/

DVDDIO

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

I2S3_FS

enabled or disabled via the PDINHIBR3 register.

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