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Chapter 11: SEU Mitigation in the Cyclone III Device Family

11–3

Automated SEU Detection

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

In user mode, Cyclone III device family supports the CHANGE_EDREG JTAG instruction,

which allows you to write to the 32-bit storage register. You can use Jam™ STAPL files

(.jam) to automate the testing and verification process. This instruction can only be

executed when the device is in user mode, and it is a powerful design feature that

enables you to dynamically verify the CRC functionality in-system without having to

reconfigure the device. You can then switch to use the CRC circuit to check for real

errors induced by an SEU.

Table 11–1 lists the CHANGE_EDREG JTAG instructions.

1 After the test completes, to clear the CRC error and restore the original CRC value,

power cycle the device or perform the following procedure:

1. After the configuration completes, use JTAG instruction CHANGE_EDREG to shift out

the correct precomputed CRC value and load the wrong CRC value to the CRC

storage register. The CRC_ERROR pin will be asserted and shows that a CRC error is

detected.

2. Use JTAG instruction CHANGE_EDREG to shift in the correct precomputed CRC value.

The CRC_ERROR pin is deasserted and shows that the error detection CRC circuitry

is working.

Automated SEU Detection

Cyclone III device family offers on-chip circuitry for automated checking of SEU

detection. Applications that require the device to operate error-free at high elevations

or in close proximity to earth’s North or South Pole require periodic checks to ensure

continued data integrity. The error detection cyclic redundancy code feature

controlled by the Device and Pin Options dialog box in the Quartus II software uses a

32-bit CRC circuit to ensure data reliability and is one of the best options for

mitigating SEU.

You can implement the error detection CRC feature with existing circuitry in

Cyclone III device family, eliminating the need for external logic. The CRC is

computed by the device during configuration and checked against an automatically

computed CRC during normal operation. The CRC_ERROR pin reports a soft error when

configuration CRAM data is corrupted, and you must decide whether to reconfigure

the FPGA by strobing the nCONFIG pin low or ignore the error.

CRC_ERROR Pin

A specific error detection pin, CRC_ERROR, is required to monitor the results of the error

detection circuitry during user mode.

Table 11–1. CHANGE_EDREG JTAG Instruction

JTAG Instruction

Instruction Code

Description

CHANGE_EDREG

00 0001 0101

This instruction connects the 32-bit CRC storage register between TDI and TDO.

Any precomputed CRC is loaded into the CRC storage register to test the operation

of the error detection CRC circuitry at the CRC_ERROR pin.

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