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CDPCLK4 Scheda tecnica(PDF) 253 Page - Altera Corporation |
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CDPCLK4 Scheda tecnica(HTML) 253 Page - Altera Corporation |
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253 / 274 page ![]() CIII51013-2.3 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Cyclone III Device Handbook Volume 1 December 2011 Subscribe ISO 9001:2008 Registered 11. SEU Mitigation in the Cyclone III Device Family Dedicated circuitry built into the Cyclone® III device family (Cyclone III and Cyclone III LS devices) consists of a cyclical redundancy check (CRC) error detection feature that can optionally check for a single-event upset (SEU) continuously and automatically. In critical applications used in the fields of avionics, telecommunications, system control, medical, and military applications, it is important to be able to: ■ Confirm the accuracy of the configuration data stored in an FPGA device ■ Alert the system to an occurrence of a configuration error This chapter describes how to activate and use the error detection CRC feature in user mode and describes how to recover from configuration errors caused by CRC error. Using the CRC error detection feature for Cyclone III device family does not impact fitting or performance. This chapter contains the following sections: ■ “Error Detection Fundamentals” on page 11–1 ■ “Configuration Error Detection” on page 11–2 ■ “User Mode Error Detection” on page 11–2 ■ “Automated SEU Detection” on page 11–3 ■ “CRC_ERROR Pin” on page 11–3 ■ “Table 11–2 lists the CRC_ERROR pin.” on page 11–4 ■ “Error Detection Block” on page 11–4 ■ “Error Detection Timing” on page 11–5 ■ “Software Support” on page 11–7 ■ “Recovering from CRC Errors” on page 11–10 Error Detection Fundamentals Error detection determines if the data received through an input device is corrupted during transmission. In validating the data, the transmitter uses a function to calculate a checksum value for the data and appends the checksum to the original data frame. The receiver uses the same calculation methodology to generate a checksum for the received data frame and compares the received checksum to the transmitted checksum. If the two checksum values are equal, the received data frame is correct and no data corruption has occurred during transmission or storage. December 2011 CIII51013-2.3 |
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