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Chapter 11: SEU Mitigation in the Cyclone III Device Family

Configuration Error Detection

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

The error detection CRC feature in Cyclone III device family puts theory into practice.

In user mode, the error detection CRC feature in Cyclone III device family ensures the

integrity of the configuration data.

Configuration Error Detection

In configuration mode, a frame-based CRC is stored in the configuration data and

contains the CRC value for each data frame.

During configuration, Cyclone III device family calculates the CRC value based on the

frame of data that is received and compares it against the frame CRC value in the data

stream. Configuration continues until either the device detects an error or all the

values are calculated.

For Cyclone III device family, the CRC is computed by the Quartus® II software and

downloaded into the device as part of the configuration bit stream. These devices

store the CRC in the 32-bit storage register at the end of the configuration mode.

User Mode Error Detection

Soft errors are changes in a configuration random-access memory (CRAM) bit state

due to an ionizing particle. Cyclone III device family has built-in error detection

circuitry to detect data corruption by soft errors in the CRAM cells.

This error detection capability continuously computes the CRC of the configured

CRAM bits based on the contents of the device and compares it with the

pre-calculated CRC value obtained at the end of the configuration. If the CRCs match,

there is no error in the current configuration CRAM bits. The process of error

detection continues until the device is reset (by setting nCONFIG to low).

The Cyclone III device family error detection feature does not check memory blocks

and I/O buffers. These device memory blocks support parity bits that are used to

check the contents of memory blocks for any error. The I/O buffers are not verified

during error detection because the configuration data uses flip-flops as storage

elements that are more resistant to soft errors. Similar flip-flops are used to store the

pre-calculated CRC and other error detection circuitry option bits.

The error detection circuitry in Cyclone III device family uses a 32-bit CRC IEEE 802

standard and a 32-bit polynomial as the CRC generator. Therefore, a single 32-bit CRC

calculation is performed by the device. If a soft error does not occur, the resulting

32-bit signature value is 0x000000, which results in a 0 on the output signal CRC_ERROR.

If a soft error occurs in the device, the resulting signature value is non-zero and the

CRC_ERROR

output signal is 1.

You can inject a soft error by changing the 32-bit CRC storage register in the CRC

circuitry. After verifying the failure induced, you can restore the 32-bit CRC value to

the correct CRC value using the same instruction and inserting the correct value.

1 Be sure to read out the correct value before updating it with a known bad value.

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