PIIX datasheet(110/122 Pages) INTEL

110 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

110

The two APM Registers are located in normal I/O space. The PIIX/PIIX3 subtractively decodes PCI accesses

to these registers and forwards the accesses to the ISA Bus. The APM Registers are not accessible by ISA

masters. Note that the remaining power management registers are located in PCI configuration space.

3.12.3.

CLOCK CONTROL

The CPU can be put in a low power state by asserting the STPCLK# signal. STPCLK# is an interrupt to the

CPU. However, for this type of interrupt, the CPU does not generate an interrupt acknowledge cycle. Once

the STPCLK# interrupt is executed, the CPU enters the stop grant state. In this state, the CPU’s internal

clocks are disabled and instruction execution is stopped. The stop grant state is exited when the STPCLK#

signal is negated.

Software can assert STPCLK#, if enabled via the SMICNTL Register, by a read of the APMC Register. Note

that STPCLK# can also be periodically asserted by using clock scaling as described below.

The PIIX/PIIX3 automatically negates STPCLK# when a break event occurs (if enabled in the SEE Register).

Software can negate STPCLK# by disabling STPCLK# in the SMICNTL Register or by a write to the APMC

Clock Scaling (Emulating Clock Division)

Clock scaling permits the PIIX/PIIX3 to periodically place the CPU in a low power state. This emulates clock

division. When clock scaling is enabled, the CPU runs at full frequency for a pre-defined time period and then

is stopped for a pre-defined time period. The run/stop time interval ratio emulates the clock division effect

from a power/performance point of view. However, clock scaling is more effective than dividing the CPU

frequency. For example, if the CPU is in the stop grant state and a break event occurs, the CPU clock returns

to full frequency. In addition, there is no recovery time latency to start the clock.

Two programmable 8-bit clock scale timer control registers set the STPCLK# high (negate) and low (assert)

times — the CTLTMRH and CTLTMRL Registers. The timer is clocked by a 32 usec internal clock. This

allows a programmable timer interval for both the STPCLK# high and low times of 0-8 msec.

3.13.

Reset Support

The PIIX/PIIX3 integrates the system reset logic for the system. The PIIX/PIIX3 generates CPURST,

PCIRST#, and RSTDRV during power up (PWROK) and when a hard reset is initiated through the RC

For the PIIX3, the PCIRST# signal is multiplexed with APICACK#. When an external IOAPIC is used, the

PCIRST# functionality is provided by externally inverting the RSTDRV signal (see Stand-Alone IOAPIC

Support section).

The following PIIX/PIIX3 signals interface directly to the processor:

CPURST

INTR

NMI

IGNNE#

SMI#

STPCLK#

These signals are open drain. Thus, external logic is not required for interfacing with the processors based on

3.3V technology which do no support 5V tolerant input buffers. During power-up these signals are driven low

to prevent problems associated with 5V/3.3V power sequencing.

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