PIIX datasheet(107/122 Pages) INTEL

107 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

107

Pentium® uni-processor or dual processor with IO-APIC: Affects systems which use Local APIC in

Virtual Wire mode of operation. This can include Intel 430HX PCIset based systems with PIIX3 and

an IO-APIC. See recommendations below.

Pentium® Pro (uni-processor or dual processor): No impact as the Pentium® Pro processor INTR

signal does not require an INTR deassertion. This includes Intel 440FX PCIset based systems with

PIIX3.

The system BIOS should incorporate one of the following recommendations:

In Dual processor systems with only a single processor installed, the Local APIC should be

disabled (placed in Bypass or Masked Mode). If a second processor is later installed, the

multiprocessing operating system may need to be reinstalled.

To overcome the minimum deassertion requirement in dual processor systems with both

processors installed, set the Pentium® processor register TR12 bit 14 to ‘1’. This solution

should be used in systems whose software uses interrupt gate or task gate interrupt handling.

This solution should not be used if the system has software with uses trap gate interrupt

handling latency times.

In dual processor systems with both processors installed, the IO-APIC can be placed into

Virtual Wire model of operation via the IO-APIC. This solution can result in increased system

interrupt handling latency times.

3.11.

X-Bus Peripheral Support

The PIIX/PIIX3 provides positive decode (chip selects) and X-Bus buffer control (XDIR# and XOE#) for a real

time clock, keyboard controller and BIOS for PCI and ISA initiated cycles. The PIIX/PIIX3 also generates

RTCALE (address latch enable) for the RTC. The chip selects are generated combinatorially from the ISA

SA(16:0) and LA (23:17) address lines (Note that it is assumed that ISA masters drive SA(19:16) and

LA(23:17) low when accessing I/O devices). The PIIX/PIIX3 also provides PS/2 mouse support via the

IRQ12/M signal and coprocessor functions (FERR# and IGNNE#). The chip selects and X-Bus buffer control

lines can be enabled/disabled via the XBCS Register.

Coprocessor Error Function

This function provides coprocessor error support for the CPU and is enabled via the XBCS Register. FERR#

is tied directly to the coprocessor error signal of the CPU. If FERR# is driven active to the PIIX, an internal

IRQ13 is generated and an the INTR output from the PIIX/PIIX3 is driven active. When a write to I/O location

F0h is detected, the PIIX/PIIX3 negates IRQ13 (internal to the PIIX) and drives IGNNE# active. IGNNE#

remains active until FERR# is driven inactive. Note, that IGNNE# is not driven active unless FERR# is active.

Mouse Function

When the mouse interrupt function is enabled (via the XBCS Register), the mouse interrupt function is

provided on the IRQ12/M input signal. In this mode, a mouse interrupt generates an interrupt through IRQ12

to the Host CPU. The PIIX/PIIX3 informs the CPU of this interrupt via a INTR. A read of 60h releases IRQ12.

If the mouse interrupt function is disabled, a read of address 60h has no effect on IRQ12/M. Reads and

writes to this register flow through to the ISA Bus. For additional information, see the IRQ12/M description in

the Signal Description.

PIIX Scheda tecnica(PDF) 107 Page - Intel Corporation

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