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FS23 Scheda tecnica(PDF) 166 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 166 Page - NXP Semiconductors |
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166 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.47 FS_I_FCCU_CFG Bit 15 14 13 12 11 10 9 8 Write - FCCU_CFG FCCU2_ASSIGN FCCU12_ FLT_POL Read 0 FCCU_CFG FCCU2_ASSIGN FCCU12_ FLT_POL Reset 0 0 0 1 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write FCCU2_ FLT_POL FCCU1_ FLT_POL FCCU2_ RSTB_IMPACT FCCU2_FS0 B_IMPACT FCCU2_ LIMP0_ IMPACT FCCU1_ RSTB_IMPACT FCCU1_FS0 B_IMPACT FCCU1_ LIMP0_ IMPACT Read FCCU2_ FLT_POL FCCU1_ FLT_POL FCCU2_ RSTB_IMPACT FCCU2_FS0 B_IMPACT FCCU2_ LIMP0_ IMPACT FCCU1_ RSTB_IMPACT FCCU1_FS0 B_IMPACT FCCU1_ LIMP0_ IMPACT Reset 0 0 1 1 1 1 1 1 Table 167. FS_I_FCCU_CFG register bit allocation Bit Symbol Description Configure FCCU1 impact on LIMP0 0 No effect 1 LIMP0 assertion 0 FCCU1_LIMP0_IMPACT POR Configure FCCU1 impact on FS0B 0 No effect 1 FS0B assertion 1 FCCU1_FS0B_IMPACT POR Configure FCCU1 impact on RSTB 0 No effect 1 RSTB assertion 2 FCCU1_RSTB_IMPACT POR Configure FCCU2 impact on LIMP0 0 No effect 1 LIMP0 assertion 3 FCCU2_LIMP0_IMPACT POR Configure FCCU2 impact on FS0B 0 No effect 1 FS0B assertion 4 FCCU2_FS0B_IMPACT POR Configure FCCU2 impact on RSTB 0 No effect 1 RSTB assertion 5 FCCU2_RSTB_IMPACT POR Configure FCCU1 fault polarity 0 Low level is a fault 1 High level is a fault 6 FCCU1_FLT_POL POR Table 168. FS_I_FCCU_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 166 / 230 |
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