FS23 datasheet(197/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

24.16 OTP_LVIO_CFG1

Bit

Write

Read

LVIO4_OUT_

DFT_OTP

LVIO3_OUT_

DFT_OTP

LVIO3PUPD_OTP

LVIO3_LS_

EN_OTP

LVIO3_HS_

EN_OTP

LVIO3_SLOT_OTP

Reset

Table 223. OTP_LVIO_CFG1 register bit allocation

Bit

Symbol

Description

Select the power sequence slot for LVIO3

00 LVIO3 polarity is changed in slot 0

01 LVIO3 polarity is changed in slot 1

10 LVIO3 polarity is changed in slot 2

11 LVIO3 is not released in a slot (enabled by SPI/I²C)

0 to 1

LVIO3_SLOT_OTP

Reset on power-on reset

Enable the HS of LVIO3

0 LVIO3 HS is disabled

1 LVIO3 HS is enabled

LVIO3_HS_EN_OTP

Reset on power-on reset

Enable the LS of LVIO3

0 LVIO3 LS is disabled

1 LVIO3 LS is enabled

LVIO3_LS_EN_OTP

Reset on power-on reset

Select the pull down on LVIO3 pin

00 LVIO3 internal pull down and pull up are configured as cell repeater

01 LVIO3 internal pull down is enabled and pull up is disabled

10 LVIO3 internal pull down is disabled and pull up is enabled

11 LVIO3 internal pull down and pull up are disabled

4 to 5

LVIO3PUPD_OTP

Reset on power-on reset

Configure the LVIO3 pin default state when LVIO3 is an output

0 LVIO3 default state is low (LS ON or LS OFF with ext. PD)

1 LVIO3 default state is high (HS ON or HS OFF with ext. PU)

LVIO3_OUT_DFT_OTP

Reset on power-on reset

Configure the LVIO4 pin default state when LVIO4 is an output

0 LVIO4 default state is low (LS ON or LS OFF with ext. PD)

1 LVIO4 default state is high (HS ON or HS OFF with ext. PU)

LVIO4_OUT_DFT_OTP

Reset on power-on reset

Table 224. OTP_LVIO_CFG1 register bit description

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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