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FS23 Scheda tecnica(PDF) 200 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 200 Page - NXP Semiconductors |
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200 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 24.19 OTP_MAIN_SYS_I2C_CFG Bit 7 6 5 4 3 2 1 0 Write Read MOD_ CONF_OTP MOD_EN_ OTP SLOT_ BYP_OTP SPI_EN_ OTP I2CDEVADDR_OTP Reset 0 0 0 0 0 0 0 0 Table 229. OTP_MAIN_SYS_I2C_CFG register bit allocation Bit Symbol Description Configure the I2C address 0000 I2C address is 0x20 0001 I2C address is 0x22 0010 I2C address is 0x24 0011 I2C address is 0x26 0100 I2C address is 0x28 0101 I2C address is 0x2A 0110 I2C address is 0x2C 0111 I2C address is 0x2E 1000 I2C address is 0x30 1001 I2C address is 0x32 1010 I2C address is 0x34 1011 I2C address is 0x36 1100 I2C address is 0x38 1101 I2C address is 0x3A 1110 I2C address is 0x3C 1111 I2C address is 0x3E 0 to 3 I2CDEVADDR_OTP[3:0] Reset on power-on reset Enable the SPI or I2C hardware pins 0 I2C pins are enabled 1 SPI pins are enabled 4 SPI_EN_OTP Reset on power-on reset Bypass the power sequence Slot 1 and Slot 2 after wake-up from LPON 0 Slot 1 and Slot 2 are not bypassed 1 Slot 1 and Slot 2 are bypassed when waking up from LPON 5 SLOT_BYP_OTP Reset on power-on reset Enable clock modulation on 20 MHz clock 0 Modulation is disabled 1 Modulation is enabled 6 MOD_EN_OTP Reset on power-on reset Select clock modulation configuration 0 Triangular modulation is selected 1 Pseudo-random modulation is selected 7 MOD_CONF_OTP Reset on power-on reset Table 230. OTP_MAIN_SYS_I2C_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 200 / 230 |
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