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FS23 Scheda tecnica(PDF) 109 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 109 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
21.1 Register map overview
Bit types
READ / WRITE
READ
WRITE
LOGIC
REGISTER
NAME
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
value
M_DEV_
CFG
0
0
CAN_EN
LIN_EN
LDTIM_EN HSD13_EN HSD24_EN
V2_EN
V1_
PNP_EN
ABIST_EN
FCCU_EN
FS0B_EN
LIMP0_EN
V0MON_
EN
0
0
OTP fuse
M_DEV_
PROG_ID
FULL_LAYER_REV
METAL_LAYER_REV
PROG_IDH
PROG_IDL
OTP fuse
M_GEN_
FLAG
0
0
0
0
0
0
0
0
HSxG
SAFETYG
PHYG
WUG
IOTIMG
COMG
VSUPG
VxG
0x0000
M_STATUS
V1
TWARN_S
LPON_S
NORMAL_
S
INIT_S
0
WK2_S
WK1_S
HVIO2_S
HVIO1_S
LVI5_S
LVIO4_S
LVIO3_S
V1_MODE
V1_S
V2_S
V3_S
0x0000
M_SYS_
CFG
0
BAT_FAIL
0
POR
0
LOCK_INIT
GO2INIT
GO2
NORMAL
GO2LPON GO2LPOFF
INT_TO_
WUEN
INTB_REQ INTB_DUR
0
MOD_
CONF
MOD_EN
OTP fuse
M_SYS1_
CFG
0
0
0
VBOS2
V1_SW_
ALWAYS_
EN
0
LOAD_
OTP_BYP
SLOT_BYP
TSLOT_
DOWN_
CFG
0
SOFTPOR_
REQ
0
DBG_EXIT
DBG_
MODE
0
OTP_EXIT
OTP_
MODE
OTP fuse
M_REG_
CTRL
0
0
0
BUCK_SRHSOFF
BUCK_SRHSON
0
0
V2ON_
LPON
V2EN
V2DIS
V3ON_
LPON
V3EN
V3DIS
OTP fuse
M_REG_
FLG
V0UV_I
V0OV_I
V1
TWARN_I
V1TSD_I
V2TSD_I
V3TSD_I
V2OL_I
V1UV_I
V2UV_I
V3UV_I
V1OV_I
V2OV_I
V3OV_I
V1OC_I
V2OC_I
V3OC_I
0x0000
M_REG_
MSK
V0UV_M
V0OV_M
V1
TWARN_M
V1TSD_M
V2TSD_M
V3TSD_M
V2OL_M
V1UV_M
V2UV_M
V3UV_M
V1OV_M
V2OV_M
V3OV_M
V1OC_M
V2OC_M
V3OC_M
0x0000
M_REG1_
FLG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V1_OCLS_I
0x0000
M_REG1_
MSK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V1_
OCLS_M
0x0000
M_IO_
CTRL
0
0
0
0
0
0
HVIO1HI
HVIO1LO
HVIO2HI
HVIO2LO
LVIO3HI
LVIO3LO
LVIO4HI
LVIO4LO
LVO6HI
LVO6LO
0x0000
M_IO_
TIMER_
FLG
0
0
0
0
0
0
0
LDT_I
LVI5_I
LVIO4_I
LVIO3_I
HVIO2_I
HVIO1_I
0
WK2_I
WK1_I
0x0000
M_IO_
TIMER_
MSK
0
0
0
0
0
0
0
LDT_M
LVI5_M
LVIO4_M
LVIO3_M
HVIO2_M
HVIO1_M
0
WK2_M
WK1_M
0x0000
M_VSUP_
COM_FLG
0
0
0
VBOS2
V1SW_S
VBOS_UV
0
I2C_CRC_I I2C_REQ_I SPI_CRC_I SPI_CLK_I SPI_REQ_I
0
VSHS_
OV_I
VSHS_
UV_I
VSUPOV_I
VSUPUV_I
0x0000
M_VSUP_
COM_MSK
0
0
0
0
0
0
I2C_
CRC_M
I2C_
REQ_M
SPI_
CRC_M
SPI_
CLK_M
SPI_
REQ_M
0
VSHS_
OV_M
VSHS_
UV_M
VSUPOV_
M
VSUPUV_
M
0x0000
M_IOWU_
CFG
LVI5_
WUCFG
LVIO4_
WUCFG
LVIO3_
WUCFG
0
HVIO2_
DGLT
HVIO1_
DGLT
WK2_DGLT WK1_DGLT
HVIO2_WUCFG
HVIO1_WUCFG
WK2_WUCFG
WK1_WUCFG
0x0005
Main
M_IOWU_
EN
0
0
LVI5_WUEN
LVIO4_WUEN
LVIO3_WUEN
HVIO2_WUEN
HVIO1_WUEN
WK2_WUEN
WK1_WUEN
0x000F
Table 74. Register map overview
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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