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FS23 Scheda tecnica(PDF) 113 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 113 Page - NXP Semiconductors |
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113 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22 SPI/I2C register description 22.1 M_DEV_CFG Bit 15 14 13 12 11 10 9 8 Write - - - - - - - - Read 0 0 CAN_EN LIN_EN LDTIM_EN HSD13_EN HSD24_EN V2_EN Reset 0 0 OTP fuse OTP fuse OTP fuse OTP fuse OTP fuse OTP fuse Bit 7 6 5 4 3 2 1 0 Write - - - - - - - - Read V1_PNP_EN ABIST_EN FCCU_EN FS0B_EN LIMP0_EN V0MON_EN 0 0 Reset OTP fuse OTP fuse OTP fuse OTP fuse OTP fuse OTP fuse 0 0 Table 75. M_DEV_CFG register bit allocation Bit Symbol Description Report the enable of VMON_EXT 0 VMON_EXT is disabled 1 VMON_EXT is enabled 2 V0MON_EN OTP fuse load Report the enable of LIMP0 0 LIMP0 is disabled 1 LIMP0 is enabled 3 LIMP0_EN OTP fuse load Report the enable of FS0B 0 FS0B is disabled 1 FS0B is enabled 4 FS0B_EN OTP fuse load Report the enable of FCCU 0 FCCU is disabled 1 FCCU is enabled 5 FCCU_EN OTP fuse load Report the enable of ABIST on demand 0 ABIST on demand is disabled 1 ABIST on demand is enabled 6 ABIST_EN OTP fuse load Report the enable of V1 PNP mode 0 V1 PNP mode is disabled 1 V1 PNP mode is enabled 7 V1_PNP_EN OTP fuse load Report the enable of V2 regulator by OTP 0 V2 regulator is disabled by OTP 1 V2 regulator is enabled by OTP 8 V2_EN OTP fuse load Table 76. M_DEV_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 113 / 230 |
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