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FS23 Scheda tecnica(PDF) 117 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 117 Page - NXP Semiconductors |
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117 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description POR, cleared when all WD flags are cleared Report a High Side event or a Cyclic Sense event HSxG = HS1_OL_I or HS1_OC_I or HS12_TSD_I or HS2_ OL_I or HS2_OC_I or HS3_OL_I or HS3_OC_I or HS34_TSD_I or HS4_OL_I or HS4_OC_I or WAKE1_OL_I or WAKE2_OL_I or HVIO1_OL_I or HVIO2_OL_I 0 No error 1 event reported 7 HSxG POR, cleared when all HSx and cyclic sense flags are cleared Table 80. M_GEN_FLAG register bit description...continued 22.4 M_STATUS Bit 15 14 13 12 11 10 9 8 Write - - - - - - - - Read V1TWARN_S LPON_S NORMAL_S INIT_S 0 WK2_S WK1_S HVIO2_S Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write - - - - - - - - Read HVIO1_S LVI5_S LVIO4_S LVIO3_S V1_MODE V1_S V2_S V3_S Reset 0 0 0 0 0 0 0 0 Table 81. M_STATUS register bit allocation Bit Symbol Description Real-time status of V1 regulator 0 V3 is disabled 1 V3 is enabled 0 V3_S Real-time information Real-time status of V2 regulator 0 V2 is disabled 1 V2 is enabled 1 V2_S Real-time information Real-time status of V1 regulator 0 V1 is disabled 1 V1 is enabled 2 V1_S Real-time information Real-time status of the HVBUCK mode or HVLDO1 mode when used with ext PNP 0 HVBUCK is in PWM mode or HVLDO1 PNP is enabled 1 HVBUCK is in PFM mode or HVLDO1 PNP is disabled 3 V1_MODE Real-time information Real-time status of LVIO3 input 0 LVIO3 is low 1 LVIO3 is high 4 LVIO3_S Real-time information Real-time status of LVIO4 input 0 LVIO4 is low 1 LVIO4 is high 5 LVIO4_S Real-time information Table 82. M_STATUS register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 117 / 230 |
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