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FS23 Scheda tecnica(PDF) 121 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 121 Page - NXP Semiconductors |
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121 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Request a software POR of FS23 (reset the digital and restart from POR) 0 No action 1 Software POR is requested 6 SOFTPOR_REQ POR, self-clear Select the power-down time slot 0 TSLOT = 2 ms 1 TSLOT = 0 ms 8 TSLOT_DOWN_CFG POR Bypass the power sequence Slot 1 and Slot 2 after wake-up from LPON 0 Slot 1 and Slot 2 are not bypassed 1 Slot 1 and Slot 2 are bypassed during power up 9 SLOT_BYP OTP fuse load Bypass the OTP loading during power up 0 OTP loading is not bypassed 1 OTP loading is bypassed 10 LOAD_OTP_BYP POR or in main FSM M4 state Control VBOS to V1 switch in Normal and LPON modes when V1 = BUCK (the switch is kept open when V1 = LDO) 0 VBOS to V1 switch is open in Normal mode 1 VBOS to V1 switch is closed in Normal and LPON mode (possible only when V1 = 5 V in Normal mode) 12 VBOS2V1_SW_ALWAYS_EN OTP fuse load Table 86. M_SYS1_CFG register bit description...continued 22.7 M_REG_CTRL Bit 15 14 13 12 11 10 9 8 Write - - - BUCK_SRHSOFF BUCK_SRHSON Read 0 0 0 BUCK_SRHSOFF BUCK_SRHSON Reset 0 0 0 OTP fuse OTP fuse Bit 7 6 5 4 3 2 1 0 Write - - V2ON_LPON V2EN V2DIS V3ON_LPON V3EN V3DIS Read 0 0 V2ON_LPON 0 0 V3ON_LPON 0 0 Reset 0 0 0 0 0 0 0 0 Table 87. M_REG_CTRL register bit allocation Bit Symbol Description Request to disable V3 0 No effect (Regulator remains in its current state) 1 Request to disable V3 0 V3DIS POR, self-clear Request to enable V3 0 No effect (Regulator remains in its current state) 1 Request to enable V3 1 V3EN POR, self-clear Table 88. M_REG_CTRL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 121 / 230 |
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