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FS23 Scheda tecnica(PDF) 151 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 151 Page - NXP Semiconductors |
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151 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Select HS4 source 0000 High side is driven by HS4_EN and HS4_DIS register bits 0001 HVIO1 is selected as direct drive pin 0010 HVIO2 is selected as direct drive pin 0011 WAKE1 is selected as direct drive pin 0100 WAKE2 is selected as direct drive pin 0101 LVIO3 is selected as direct drive pin 0110 LVIO4 is selected as direct drive pin 0111 LVI5 is selected as direct drive pin 1000 High side is driven by TIMER1 1001 High side is driven by TIMER2 1010 High side is driven by TIMER3 1011 High side is driven by PWM1 1100 High side is driven by PWM2 1101 High side is driven by PWM3 1110 Not used 1111 Not used 12 to 15 HS4_SRC_SEL POR or HS4 FSM in HS2 state Table 136. M_HSx_SRC_CFG register bit description...continued 22.32 M_HSx_CTRL Bit 15 14 13 12 11 10 9 8 Write - HS_ VSHSUVOV_ REC HS_ VSHSUV_DIS HS_ VSHSOV_DIS - - - - Read 0 HS_ VSHSUVOV_ REC HS_ VSHSUV_DIS HS_ VSHSOV_DIS 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write - HS4_EN - HS3_EN - HS2_EN - HS1_EN Read 0 HS4_EN 0 HS3_EN 0 HS2_EN 0 HS1_EN Reset 0 0 0 0 0 0 0 0 Table 137. M_HSx_CTRL register bit allocation Bit Symbol Description Enable the HS1 0 HS1 is disabled 1 HS1 is enabled 0 HS1_EN POR or HS1 FSM in HS2 state Enable the HS2 0 HS2 is disabled 1 HS2 is enabled 2 HS2_EN POR or HS2 FSM in HS2 state Table 138. M_HSx_CTRL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 151 / 230 |
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