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FS23 Scheda tecnica(PDF) 148 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 148 Page - NXP Semiconductors |
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148 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.30 M_CS_FLG_MSK Bit 15 14 13 12 11 10 9 8 Write - - - - - - - HVIO2_OL_M Read 0 0 0 0 0 0 0 HVIO2_OL_M Reset 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 Write[1] HVIO1_OL_M WAKE2_OL_M WAKE1_OL_M - HVIO2_OL_I HVIO1_OL_I WAKE2_OL_I WAKE1_OL_I Read HVIO1_OL_M WAKE2_OL_M WAKE1_OL_M 0 HVIO2_OL_I HVIO1_OL_I WAKE2_OL_I WAKE1_OL_I Reset 0 0 0 0 0 0 0 0 Table 133. M_CS_FLG_MSK register bit allocation [1] Write 1 in a flag to clear it. Bit Symbol Description Report WAKE1 open-load event 0 No event detected 1 WAKE1 OL occurred 0 WAKE1_OL_I POR, or clear on write (write '1') Report WAKE2 open-load event 0 No event detected 1 WAKE2 OL occurred 1 WAKE2_OL_I POR, or clear on write (write '1') Report HVIO1 open-load event 0 No event detected 1 HVIO1 OL occurred 2 HVIO1_OL_I POR, or clear on write (write '1') Report HVIO2 open-load event 0 No event detected 1 HVIO2 OL occurred 3 HVIO2_OL_I POR, or clear on write (write '1') Inhibit WAKE1 open-load interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 5 WAKE1_OL_M POR Inhibit WAKE2 open-load interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 6 WAKE2_OL_M POR Inhibit HVIO1 open-load interrupt 0 Interrupt is not inhibited 1 Interrupt is inhibited 7 HVIO1_OL_M POR Inhibit HVIO2 open-load interrupt 0 Interrupt is not inhibited 8 HVIO2_OL_M 1 Interrupt is inhibited Table 134. M_CS_FLG_MSK register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 148 / 230 |
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