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FS23 Scheda tecnica(PDF) 149 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 149 Page - NXP Semiconductors |
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149 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description POR Table 134. M_CS_FLG_MSK register bit description...continued 22.31 M_HSx_SRC_CFG Bit 15 14 13 12 11 10 9 8 Write HS4_SRC_SEL HS3_SRC_SEL Read HS4_SRC_SEL HS3_SRC_SEL Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HS2_SRC_SEL HS1_SRC_SEL Read HS2_SRC_SEL HS1_SRC_SEL Reset 0 0 0 0 0 0 0 0 Table 135. M_HSx_SRC_CFG register bit allocation Bit Symbol Description Select HS1 source 0000 High side is driven by HS1_EN and HS1_DIS register bits 0001 HVIO1 is selected as direct drive pin 0010 HVIO2 is selected as direct drive pin 0011 WAKE1 is selected as direct drive pin 0100 WAKE2 is selected as direct drive pin 0101 LVIO3 is selected as direct drive pin 0110 LVIO4 is selected as direct drive pin 0111 LVI5 is selected as direct drive pin 1000 High side is driven by TIMER1 1001 High side is driven by TIMER2 1010 High side is driven by TIMER3 1011 High side is driven by PWM1 1100 High side is driven by PWM2 1101 High side is driven by PWM3 1110 Not used 1111 Not used 0 to 3 HS1_SRC_SEL POR or HS1 FSM in HS2 state Table 136. M_HSx_SRC_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 149 / 230 |
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