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FS23 Scheda tecnica(PDF) 147 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 147 Page - NXP Semiconductors |
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147 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.29 M_CS_CFG Bit 15 14 13 12 11 10 9 8 Write - - - - - - HS_FLT_ WU_FORCE - Read 0 0 0 0 0 0 HS_FLT_ WU_FORCE 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write HVIO2_HS_SEL HVIO1_HS_SEL WK2_HS_SEL WK1_HS_SEL Read HVIO2_HS_SEL HVIO1_HS_SEL WK2_HS_SEL WK1_HS_SEL Reset 0 0 0 0 0 0 0 0 Table 131. M_CS_CFG register bit allocation Bit Symbol Description Select the high-side connected to WAKE1 for cyclic sensing 00 HS1 is connected to WAKE1 01 HS2 is connected to WAKE1 10 HS3 is connected to WAKE1 11 HS4 is connected to WAKE1 0 to 1 WK1_HS_SEL POR Select the high-side connected to WAKE2 for cyclic sensing 00 HS1 is connected to WAKE2 01 HS2 is connected to WAKE2 10 HS3 is connected to WAKE2 11 HS4 is connected to WAKE2 2 to 3 WK2_HS_SEL POR Select the high-side connected to HVIO1 for cyclic sensing 00 HS1 is connected to HVIO1 01 HS2 is connected to HVIO1 10 HS3 is connected to HVIO1 11 HS4 is connected to HVIO1 4 to 5 HVIO1_HS_SEL POR Select the high-side connected to HVIO2 for cyclic sensing 00 HS1 is connected to HVIO2 01 HS2 is connected to HVIO2 10 HS3 is connected to HVIO2 11 HS4 is connected to HVIO2 6 to 7 HVIO2_HS_SEL POR Select the reaction when a fault is detected on a high-side 0 Disable the cyclic sense engine when the fault is present 1 Force the wake-up of the device when the fault is detected 9 HS_FLT_WU_FORCE POR Table 132. M_CS_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 147 / 230 |
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